ANALYSIS TYPE / 06
IC package · board PDN · co-optimisation
Overview
Co-simulating IC package and board PDN together to capture the interaction between on-package capacitance, package plane inductance, and board-level decoupling — providing a complete system-level power integrity assessment.
Deliverables
Key Aspects
Incorporating vendor-provided IC package S-parameter or SPICE models into the board-level PDN simulation to capture the complete power delivery path from VRM to silicon.
Evaluating the contribution of on-package decoupling capacitors to board-level PDN impedance, determining how much additional board decoupling is required versus package-integrated capacitance.
Identifying resonances introduced by the interaction between package and board PDN structures — particularly the inductance of the package-to-board interface vias and balls.
Optimising the combined package and board decoupling strategy as a unified system, minimising total capacitor count and cost while meeting package-level and board-level impedance targets.
Connect with our power integrity team to discuss the right approach for your application.
