ANALYSIS TYPE / 02
capacitor selection · placement · anti-resonance
Overview
Optimising decoupling capacitor selection, value, quantity, and placement to flatten the PDN impedance profile — avoiding anti-resonance peaks while achieving the minimum capacitor count and cost for each power domain.
Deliverables
Key Aspects
Selecting optimal capacitance values and ESR/ESL profiles to fill specific frequency bands in the impedance profile, minimising total component count without sacrificing performance.
Determining capacitor placement relative to IC power pins, via positions, and reference planes to minimise loop inductance and maximise decoupling effectiveness at operating frequencies.
Identifying and resolving anti-resonance peaks between bulk and ceramic capacitor stages that cause localised impedance spikes exceeding target impedance at specific frequencies.
Iterating the decoupling strategy to achieve specification compliance with the fewest, lowest-cost capacitors — balancing SI performance against PCB area and bill of materials budget.
Connect with our power integrity team to discuss the right approach for your application.
