ANALYSIS TYPE / 01
target impedance · frequency response · Z-profile
Overview
Characterising power delivery network impedance across the full frequency range — from DC through multi-GHz — to ensure the impedance profile remains below the target impedance budget for all IC power domains on the board.
Deliverables
Key Aspects
Computing the maximum allowable PDN impedance for each power rail based on IC load current transients, supply voltage tolerance, and acceptable ripple budgets.
Simulating PDN impedance versus frequency including VRM, bulk capacitors, ceramic bypass capacitors, and PCB plane inductance — identifying resonant peaks that exceed targets.
Analysing multiple power domains simultaneously to identify coupling between adjacent power planes and shared return paths that degrade power integrity performance.
Correlating simulated PDN impedance with physical VNA measurements for model validation and iterative design improvement before final board release.
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