Pre/post-layout · channel analysis · eye diagram · PDN compliance
Pre and post-layout signal integrity analysis covering impedance profiling, crosstalk evaluation, eye diagram compliance, and power delivery network characterisation — from schematic to final PCB at multi-GHz data rates.
What We Deliver
Signal integrity failures are among the most costly and difficult to debug post-production. Our signal integrity team identifies impedance discontinuities, reflections, and crosstalk paths during the design phase — before PCB fabrication — enabling targeted corrections that prevent bit errors, margin failures, and EMI issues at multi-GHz data rates.
We support both pre-layout analysis and post-layout verification across SerDes, DDR, USB, PCIe, and custom high-speed interfaces — from early topology decisions through to design sign-off.
Key Problems We Solve
6 Analysis Areas
Select a capability to explore the methodology, deliverables, and tools in detail.
ANALYSIS TYPE / 01
stack-up · routing rules · topology planning
Establishing impedance targets, layer stack constraints, differential pair spacing rules, and via design guidelines before routing begins — preventing costly design rework after tape-out by setting correct SI parameters from day one.
Key Aspects
Defining dielectric materials, copper weights, and layer sequence to achieve target differential and single-ended impedances across the full operating frequency range.
Computing controlled impedance values for all critical net classes — LVDS, DDR, SerDes, USB — and establishing tolerance budgets for PCB fabrication.
Translating SI simulation results into DRC-enforceable routing rules: trace width, spacing, length matching, and reference plane requirements.
Building accurate via and connector models using field-solver data, establishing via stubs, back-drill requirements, and connector launch optimisation.
ANALYSIS TYPE / 02
reflection · insertion loss · mismatch analysis
Identifying vias, connectors, bends, reference plane gaps, and stubs that create impedance mismatches — quantifying reflection and insertion loss penalties at operating frequency and providing targeted redesign guidance.
Key Aspects
Computing resonant frequency penalties from unterminated via stubs and defining back-drill depth requirements to remove insertion loss at target data rates.
Simulating connector launch geometries to match source impedance, minimising reflections at board-to-connector interfaces in high-speed assemblies.
Identifying split planes, anti-pads, and routing across gaps that cause impedance excursions and return current disruption on critical signal nets.
Extracting broadband S-parameter models of discontinuities for system-level channel simulation and correlation with physical measurement data.
ANALYSIS TYPE / 03
NEXT · FEXT · spacing · shielding
Computing near-end (NEXT) and far-end (FEXT) crosstalk between adjacent signal traces and differential pairs — defining required spacing, return current management, and guard trace strategy for reliable high-density routing.
Key Aspects
Simulating forward and backward crosstalk induced on victim nets as a function of aggressor amplitude, routing length, and layer separation.
Identifying the most critical aggressor-victim net pairs in dense routing areas and ranking coupling severity to prioritise layout changes.
Determining minimum trace separation to maintain crosstalk below budget values for each interface class — balancing SI performance with routing density.
Quantifying noise reduction achieved by guard traces and stitching vias, and identifying cases where guard traces offer marginal benefit versus routing space cost.
ANALYSIS TYPE / 04
BER · margin · jitter decomposition
Simulating complete channel performance at the target bit rate — generating statistical eye diagrams, BER estimates, and full jitter decomposition to evaluate mask compliance and identify margin-limiting contributors.
Key Aspects
Constructing statistical eye diagrams via IBIS-AMI or channel simulation for realistic bit-rate performance assessment, including ISI, random jitter, and deterministic jitter contributions.
Decomposing total jitter into deterministic, random, and bounded uncorrelated components — attributing margin loss to specific physical root causes in the channel.
Projecting bit error rate at target operating margin to confirm compliance with interface specifications such as PCIe, USB 3.x, and DDR eye mask requirements.
Evaluating CTLE, FFE, and DFE equaliser settings to maximise eye opening and determine the optimal TX/RX equalization strategy for the channel under analysis.
ANALYSIS TYPE / 05
PCIe · USB · DDR4/5 · equalisation
Validating PCIe, USB 3.x, HDMI, DDR4/5, and custom SerDes channels against specification-defined eye masks and jitter budgets — including full equalisation optimisation and compliance margin reporting.
Key Aspects
Mapping simulation results to PCIe, USB, HDMI, SATA, and custom SerDes compliance test points and mask definitions for pre-silicon channel sign-off.
Performing full DDR4 and DDR5 timing analysis including tDQSQ, tQH, read/write levelling, and fly-by topology validation across voltage and temperature corners.
Quantifying design margin above specification limits and identifying which channel segments consume the most margin budget for targeted improvement.
Validating boards carrying multiple high-speed protocols — ensuring each interface achieves compliance simultaneously without inter-protocol interference.
ANALYSIS TYPE / 06
extracted parasitics · Gerber verification · design sign-off
Extracting full-board S-parameter models from final Gerber data and verifying that the routed design meets all SI targets before prototype builds — providing design sign-off confidence backed by field-solver-accurate simulation.
Key Aspects
Performing full parasitic extraction from final layout data — including coupled inductance, capacitance, and resistance — for accurate post-route SI simulation.
Converting fabrication-ready Gerber and ODB++ data into 3D EM models, closing the gap between design intent and manufactured geometry.
Generating a formal SI sign-off report before prototype build authorisation — documenting all interfaces, margins, and outstanding risks.
Correlating post-layout simulation results with physical measurement data from lab characterisation to validate model accuracy and refine simulation methodology.
Talk to our Centre of Excellence team about pre-layout rule definition, post-layout verification, or eye diagram compliance for your high-speed design.
