ANALYSIS TYPE / 02
reflection · insertion loss · mismatch analysis
Overview
Identifying vias, connectors, bends, reference plane gaps, and stubs that create impedance mismatches — quantifying reflection and insertion loss penalties at operating frequency and providing targeted redesign guidance.
Deliverables
Key Aspects
Computing resonant frequency penalties from unterminated via stubs and defining back-drill depth requirements to remove insertion loss at target data rates.
Simulating connector launch geometries to match source impedance, minimising reflections at board-to-connector interfaces in high-speed assemblies.
Identifying split planes, anti-pads, and routing across gaps that cause impedance excursions and return current disruption on critical signal nets.
Extracting broadband S-parameter models of discontinuities for system-level channel simulation and correlation with physical measurement data.
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