ANALYSIS TYPE / 01
stack-up · routing rules · topology planning
Overview
Establishing impedance targets, layer stack constraints, differential pair spacing rules, and via design guidelines before routing begins — preventing costly design rework after tape-out by setting correct SI parameters from day one.
Deliverables
Key Aspects
Defining dielectric materials, copper weights, and layer sequence to achieve target differential and single-ended impedances across the full operating frequency range.
Computing controlled impedance values for all critical net classes — LVDS, DDR, SerDes, USB — and establishing tolerance budgets for PCB fabrication.
Translating SI simulation results into DRC-enforceable routing rules: trace width, spacing, length matching, and reference plane requirements.
Building accurate via and connector models using field-solver data, establishing via stubs, back-drill requirements, and connector launch optimisation.
Connect with our signal integrity team to discuss the right approach for your application.
